Field of Invention
The present invention relates to a complementary metal oxide semiconductor (CMOS) device with dual-wells and a manufacturing method thereof; particularly, it relates to such a CMOS device with dual-wells having a reduced conduction resistance and an increased breakdown voltage, and a manufacturing method thereof.
Description of Related Art
FIG. 1 shows a cross-section view of a prior art complementary metal oxide semiconductor (CMOS) device 100, which includes: a P-type substrate 101, an epitaxial layer 102, a P-type well 103a, an N-type well (N-well) 103b, an isolation region 104, N-type lightly doped diffusion (NLDD) regions 105a and 105b, P-type lightly doped diffusion (PLDD) regions 105c and 105d, an N-type source 106a, a P-type source 106b, an N-type drain 107a, a P-type drain 107b, a P-type body region 108a, an N-type body region 108b, and gates 111a and 111b. The isolation region 104 is formed by local oxidation of silicon (LOCOS), to define an NMOS operation region 104a and a PMOS operation region 104b, which are major operation regions of the CMOS device 100. The operation regions 104a and 104b are indicated by the solid arrows shown in FIG. 1. The CMOS device 100 includes the NMOS operation region 104a and the PMOS operation region 104b. In the NMOS operation region 104a, the N-type source 106a and the NLDD region 105a are at one side with respect to the gate 111a, and are connected to each other; the N-type drain 107a and the NLDD region 105b are at the other side with respect to the gate 111a, and are connected to each other. The two connected regions at two sides of the gate 111a are separated by the P-type well 103a. Similarly, in the PMOS operation region 104b, the P-type source 106b and the PLDD region 105c are at one side with respect to the gate 111b, and are connected to each other; the P-type drain 107b and the PLDD region 105d are at the other side with respect to the gate 111b, and are connected to each other. The two connected regions at two sides of the gate 111b are separated by the N-type well 103b. 
An important trend in the field of semiconductor device is to reduce the device size; however, as the channel of the CMOS device is shortened, a short channel effect (SCE) caused by drain-induced barrier lowering (DIBL) and hot carrier effect (HCE) will occur. The details of these effects are well-known by one skilled in the art, so they are not redundantly explained here.
As an example, for a CMOS device having a gate operation voltage of 5V, when the gate length is shorter than 0.6 μm, the SCE starts to occur. Because of the SCE, the gate length cannot be shorter, unless some solution is proposed to solve this SCE effect. That is, an effective solution is required for a CMOS device to be able to operate under certain given operation voltage, and integrated with other devices (or connected in parallel with other CMOS devices of the same characteristics) in a circuit, without SCE, while with a reduced size.
In view of above, to overcome the drawbacks in the prior art, the present invention proposes a dual-well CMOS device having a reduced conduction resistance and an increased breakdown voltage, and a manufacturing method thereof.